1. Field of the Invention
This invention relates to methods for manufacturing functional multilayer devices on dimensionally unstable substrates, in particular manufacturing of electronic switching devices on flexible, plastic substrates; and to devices fabricated by these methods.
2. Description of Related Art
Integration of functional, electronic devices onto flexible substrates will potentially enable new electronic products such as flexible displays, or low-cost intelligent labels, as well as new manufacturing approaches, such as roll-to-roll manufacturing. To manufacture practical electronic devices it is critical that the components of the devices defined in different layers are registered accurately with respect to each other. This is particularly important for manufacturing of thin-film transistors (TFTs). FIG. 1A shows a schematic diagram of a top-gate TFT according to the prior art. On a substrate (1) source (2) and drain (3) electrodes are defined with a separation distance L. In order to achieve the performance requirements for most TFT applications L needs to be on the order of 2-10 μm or less. A semiconducting layer (4), and a dielectric layer (5) are formed on top. A gate electrode (6) needs to be accurately aligned with respect to the source-drain electrodes. The gate electrode needs to overlap with the semiconducting channel of length L of the device in order to be able to control effectively the current flow in the active region of the device. Furthermore, the overlap regions of length dgs and dgd between the gate electrode and the source and drain electrodes need to be controlled very precisely. The overlap regions determine the parasitic gate-source and gate-drain overlap capacitance Cgs and Cgd, respectively. These should generally be as small as possible to improve the switching speed of the TFTs and minimize unwanted capacitive coupling effects. In an active matrix display (FIG. 1B) Cgs is particularly important as it determines the capacitive coupling between the signals running along the gate lines and the pixel electrode. When the gate voltage is switched to turn off the TFT at the end a particular addressing cycle Cgs causes the voltage on the pixel to follow the gate voltage. This so-called kickback voltage changes the pixel voltage from the intended value to which the pixel had been charged with the signal on the data line.
This problem with parasitic capacitance becomes particularly severe when Cgs is large and exhibits variations across the active matrix of TFTs. In this case the kickback voltage is different between different pixels of the display, and induces undesired variations in optical contrast across the display, that cannot easily be compensated for (E. Lueder, Liquid Crystal Displays, John Wiley & Sons, New York (2001)). Background prior art relating to printing onto a glass LED substrate can be found in US 2002/132398 and US 2003/0148560.
The problem is, however, particularly difficult with flexible substrates, such as plastic substrates. Plastic substrates exhibit significant dimensional changes when subject to mechanical stress or temperature variations both of which occur during any manufacturing process. When a plastic substrate such as a thin sheet of polyethyleneterephtalate (PET) is heated it tends to shrink, and therefore the dimension of any pattern which has been defined on the substrate is changing as a result of the heat exposure. Given an arbitrary reference point on such a pattern one can define an absolute distortion field, which attaches to every feature on the substrate a distortion vector equal to the difference vector of the actual position of the feature on the substrate with respect to the reference point and its nominal position that was intended when the pattern was defined. The nominal position can, for example, be determined by a pattern on a photomask that is transferred one-to-one onto the substrate using a photolithographic process.
For many low-cost, flexible substrates such as PET or polyethylenenaphtalate (PEN) typical absolute distortions on a substrate with a dimension of 12-14″ are on the order of 50-100 μm. Such distortions cause severe problems in a manufacturing process which requires definition of multiple patterns on top of each other with good registration of the features of an upper pattern to the features of a previously defined pattern over a large substrate area. If two patterns are defined without taking into account the distortion of the substrate which has occurred in between the two patterning steps, the relative position of the upper pattern with respect to the lower pattern will differ between devices in different regions of the substrate. If the substrates distorts in between two such lithographic patterning step, the second pattern will not match the previous one. This will cause variations of the parasitic capacitance in different regions of the substrate. In extreme cases the TFT gate electrode might not even overlap with the channel. This problem is illustrated in FIG. 2, where it is assumed that the bottom source-drain layer 7 has been distorted, such that the gate electrode and interconnect pattern 8 which is supposed to match accurately the source-drain pattern is out-of-registration in some regions of the substrate.